1. Field of the Invention
The present invention generally relates to a data processing device, a signal processing device and an interface device. More particularly, the present invention relates to a data processing device that performs data input/output operations based on a stored program of a hard disk drive, and the present invention also relates to a signal processing device that selectively outputs one of testing signals of an internal logic circuit of a hard disk drive, and further the present invention relates to an interface device that performs data input/output operations in a hard disk drive via a plurality of channels.
2. Description of the Related Art
FIG. 1 shows a configuration of a hard disk drive.
As shown in FIG. 1, the hard disk drive 1 generally includes an enclosure 2 and a circuit board 3. In the enclosure 2, a disk 11, a spindle motor (SPM) 12, a magnetic head 13, a voice coil motor (VCM) 14, and a head IC (HDIC) 15 are provided. The disk 11 is rotated by the spindle motor 12. The head 13 is placed on the surface of the disk 11 such that the head 13 confronts the disk surface. The head 13 is attached to the voice coil motor 14, and the head 13 is movable in a radial direction of the disk 11 by the voice coil motor 14. The head 13 magnetizes the disk 11 in accordance with writing information. The head 13 outputs a signal indicative of the magnetized condition of the disk 11 to the head IC 15.
In the hard disk drive 1 of FIG. 1, the spindle motor 12 is rotated in response to a rotation control signal supplied from the circuit board 3. The voice coil motor 14 is actuated in response to a position control signal supplied from the circuit board 3, and the voice coil motor 14 performs the positioning of the head 13 relative to the disk 11. The head 13 magnetizes the disk 11 in accordance with writing information sent from the circuit board 3, and the head 13 sends a read-out signal to the head IC 15, the read-out signal being produced from the disk 11 in response to the magnetized condition of the disk 11. The head IC 15 amplifies the writing signal, sent by the circuit board 3, and sends the amplified writing signal to the head 13. The head IC 15 amplifies the read-out signal, sent by the head 13, and sends the amplified read-out signal to the circuit board 3.
In the hard disk drive 1 of FIG. 1, the circuit board 3 generally includes a read channel 21, a hard disk controller (HDC) 22, a buffer memory 23, a servo controller 24, and a ROM (read-only memory) 25. The read channel 21 generates a writing signal based on writing information from the hard disk controller 22, and generates a read-out data based on the read-out signal sent from the head 13. Moreover, the read channel 21 extracts a servo signal from the read-out signal sent from the head 13, and sends the servo signal to the servo controller 24.
The servo controller 24 controls the rotation of the spindle motor 12 and the actuation of the voice coil motor 14 based on the servo signal from the read channel 21. The ROM 25 stores, in advance, the program codes (or the firmware) that are executed by a processor of the hard disk controller 22. When the hard disk drive is powered on, the program codes of the ROM 25 are loaded to the internal memory of the hard disk controller 22, and the program codes are executed by the processor of the hard disk controller 22.
FIG. 2 shows a configuration of a conventional hard disk controller for use in the hard disk drive.
As shown in FIG. 2, the conventional hard disk controller 22 generally includes an interface unit 31, a buffer manager 32, a disk formatter 33, a processor 34, and a program memory 35. The elements 31 to 35 of the hard disk controller 22 are interconnected by a bus as indicated in FIG. 2.
In the conventional hard disk controller 22, the interface unit 31 provides the interface between the hard disk controller 22 and a host computer 41 when receiving writing data from the host computer 41. The buffer manager 32 temporarily stores the writing data, received from the host computer 41, into the buffer memory 23. The buffer manager 32 reads the writing data from the buffer memory 23 and delivers the writing data to the disk formatter 33, based on the command from the processor 34. The disk formatter 33 formats the writing data of the buffer memory 23 in a predetermined format and delivers the formatted writing data to the read channel 21 based on the command from the processor 34.
Further, in the conventional hard disk controller 22, the read-out data from the read channel 21 is received at the disk formatter 33, and the disk formatter 33 reconstructs the read-out data in the original format and delivers the resulting read-out data to the buffer manager 32. The buffer manager 32 stores the read-out data, received from the disk formatter 33, into the buffer memory 23. The buffer manager 32 reads the read-out data from the buffer memory 23 and delivers the read-out data to the host computer 41 via the interface unit 31 based on the command from the processor 34.
In the conventional hard disk controller 22, the processor 34 executes the program codes of the firmware that are loaded from the ROM 25 into the program memory 35. Hence, the conventional hard disk controller 22 is required to load the program codes of the firmware from the ROM 25 into the program memory 35 in order to allow the processor 34 to execute the program codes of the firmware. Further, the conventional hard disk controller 22 is required that the buffer memory 23 be externally connected to the conventional hard disk controller 22 in order to allow the buffer memory 23 to temporarily store the writing data or the read-out data.
Generally, the firmware stored in the conventional hard disk controller 22 may be classified into two categories: the firmware with high-level functions and the firmware with low-level functions. The number of processing steps and the number of usable parameters included in the firmware with high-level functions are larger than those in the firmware with low-level functions. With the use of the firmware with high-level functions, the hard disk drive can be controlled so as to achieve the high-level functions of the hard disk drive. In addition, the number of processing steps and the number of usable parameters included in the firmware with low-level functions are smaller than those in the firmware with high-level functions. When the firmware with low-level functions is stored in the conventional hard disk controller 22, the processing steps can be executed with relatively low cost.
The hard disk controller 22 including the program memory 35 is usually constructed into a single chip. Generally, when an internal memory is included in a multi-function LSI, the area of the memory included in the chip is large, and the area of the entire chip is increased. This is detrimental to the construction of smaller-size chip, or the yield is lowered. For this reason, it is required to make the amount of storage of the memory at the necessary, minimum level.
Conventionally, the hard disk controller including the firmware with high-level functions and the hardware including the firmware with low-level functions are provided with the internal memories with different amounts of storage. By using such configuration, the amount of storage of the internal memories is made at the necessary, minimum level, thereby preventing the construction of a large-size chip.
The conventional hard disk controller 22 shown in FIG. 2 is provided for use in the hard disk drive. In the case of the conventional hard disk controller 22, the chip containing the firmware with high-level functions and the chip containing the firmware with low-level functions are separately designed and developed. For this reason, the manufacturing cost is considerably increased.
Next, a description will be given of a method of testing an LSI for use in the hard disk drive.
FIG. 3 shows a configuration of an LSI which is provided in the hard disk drive. As shown in FIG. 3, the conventional LSI 50 generally includes an internal logic circuit 51 and a multiplexer 52. The internal logic circuit 51 performs a given logic operation for input signals that are received from input terminals “Tin 1” through “Tin n” of the LSI 50, and outputs the processed signals to output terminals “Tout 1” through “Tout m” of the LSI 50, respectively. The internal logic circuit 51 is comprised of a plurality of blocks (#1 through #p), and the respective testing signals from the blocks #1 through #p of the internal logic circuit 51 are transferred to the multiplexer 52. A select pattern of “p” select signals that are received from test select terminals “Ts1” through “Tsp” of the LSI 50 is supplied to the multiplexer 52. The multiplexer 52 selects one of the testing signals from the blocks #1 through #p of the internal logic circuit 51 based on the select pattern from the test select terminals “Ts1” through “Tsp”, and sends the selected testing signal to a test output terminal “Ttout” of the LSI 50.
FIG. 4 is a time chart for explaining operation of the conventional LSI 50 during a test. In FIG. 4, (A) indicates an internal clock of the LSI 50, (B) indicates an output signal of the block #3, (C) indicates an output signal of the block #5, (D) indicates the select pattern, and (E) indicates an output signal of the test output terminal “Ttout”.
As indicated in FIG. 4(A), the respective signals from the blocks #1 through #p of the internal logic circuit 51 are output synchronously with the rising edge of the internal clock. As indicated in FIG. 4(D), at time “t1” the select pattern from the test select terminals “Ts1” through “Tsp”, which indicates the selection to select the block #3 signal, is input to the multiplexer 52. At time “t2”, which matches with the time of the following rising edge of the internal clock, the multiplexer 51 outputs the block #3 signal to the test output terminal “Ttout”, as indicated in FIG. 4(E), based on the select signal. The block #3 signal, output to the test output terminal “Ttout” at this time, is the same as the block #3 signal indicated in FIG. 4 (B).
Further, at time “t3” the select pattern from the test select terminals “Ts1” through “Tsp”, which indicates the selection to select the block #5 signal, is input to the multiplexer 52, as indicated in FIG. 4(D). At time “t4”, which matches with the time of the following rising edge of the internal clock, the multiplexer 51 outputs the block #5 signal to the test output terminal “Ttout”, as indicated in FIG. 4(E), based on the select signal. The block #5 signal, output to the test output terminal “Ttout” at this time, is the same as the block #5 signal indicated in FIG. 4(C).
As described above, in the conventional LSI testing method, the selected testing signal, which is selected from among the respective testing signals of the internal logic circuit 51 based on the select pattern from the test select terminals of the LSI 50, is output to the test output terminal “Ttout”.
In the above-described LSI testing method, the select pattern sent from the test select terminals of the LSI 50 must be provided to indicate all of the testing signals of the blocks of the internal logic circuit 51 for outputting the selected testing signal to the test output terminal. The LSI 50 requires a large number of the test select terminals for the testing of the internal logic circuit 51. This is detrimental to the construction of smaller-size chip.
Next, a description will be given of a method of data transfer of a conventional interface device.
FIG. 5 shows a configuration of an interface device for use in the hard disk drive. As shown in FIG. 5, the conventional interface device 60 generally includes an interface circuit (IF A) 61, an interface circuit (IF B) 62, a data buffer memory 63, a buffer controller 64, and a hard disk controller (HDC) 65.
In the conventional interface device 60, the interface circuit 61 provides the interface between the hard disk drive and a computer A, and the interface circuit 62 provides the interface between the hard disk drive and a computer B. The buffer controller 64 stores the input data, received from the interface circuit 61 or the interface circuit 62, into the data buffer memory 63. The buffer controller 64 reads data, which is to be recorded to the magnetic disk 11, from the data buffer memory 63, and transmits the data to the magnetic head 13 through the HDC 65. The data is recorded to the disk 11 by means of the head 13.
Further, in the conventional interface device 60, the read-out signal, which is output by the head 13 of the hard disk drive when reading data from the disk 11, is received at the HDC 65. The HDC 65 produces the read-out data from the received read-out signal, and sends the read-out data to the buffer controller 64. The buffer controller 64 temporarily stores the read-out data, which is received from the HDC 65, into the data buffer memory 63. The buffer controller 64 sends the read-out data, read from the data buffer memory 63, to one of the computers A and B via one of the interface circuits 61 and 62.
In the conventional interface device 60, the interface circuit 61 and the interface circuit 62 share the data buffer memory 63, and the interface that can operate simultaneously is restricted by the data transfer capacity of the data buffer memory 63. For example, suppose that the data transfer capacity of the buffer memory 63 is 350 MB/s, and the data transfer capacity of each of the interface circuits 61 and 62 is 200 MB/s. In such a case, when one of the interface circuits 61 and 62 operates to transfer the data from the data buffer memory 63 to one of the computers A and B, the other interface circuit does not operate due to the data transfer capacity of the data buffer memory 63 and is set in a waiting condition until the data transfer of the former interface circuit is done. Hence, because of the data transfer capacity of the buffer memory 63, it is difficult for the conventional interface device 60 to simultaneously carry out the data reading/writing operations with the buffer memory 63.
The commands from the computer A or the computer B are linked to the command queue in the interface circuit 61 or the interface circuit 62, and retained in the interface circuit 61 or the interface circuit 62. The incoming commands are linked to the command queue in order of their arrivals, and the commands in the command queue are re-ordered such that the movement of the head 13 needed to execute each command is minimized. The re-ordering of the commands is performed such that, when the write command and the read command are related to the same sector of the disk 11, the write command is set at a preceding position of the command queue and the read command is set at a following position of the command queue. If the write command is set at a position of the command queue following the position of the read command by the re-ordering, the read command is executed at a too early time, and the non-updated data before the writing data is recorded to the disk 11 is improperly read from the disk 11 by the early execution of the read command.
When the read command from one of the computers A and B is received at one of the interface circuits 61 and 62, the read-out signal, which is output by the head 13 when reading data from the disk 11, is received at the HDC 65. The HDC 65 produces the read-out data from the received read-out signal, and sends the read-out data to the buffer controller 64. The buffer controller 64 temporarily stores the read-out data, which is received from the HDC 65, into the data buffer memory 63. The buffer controller 64 transfers the read-out data, read from the data buffer memory 63, to one of the computers A and B via one of the interface circuits 61 and 62.
When it is expected that a subsequent read command related to the same sector of the disk 11 is issued, the read-out data of the buffer memory 63 is retained until the execution of the subsequent read command starts. The buffer controller 64 transfers the retained read-out data from the buffer memory 63 to the command source (one of the computers A and B) without reading the data from the disk 11 again. This procedure is called the cache processing, and the buffer memory 63 in this case is called the cache memory. According to the cache processing, the conventional interface device 60 can considerably reduce the total time needed to execute the read commands related to the same sector of the disk 11.
In the conventional interface device 60, when the cache processing is performed, a cache table that provides the correlations between the locations of data stored on the buffer memory 63 and the locations of data stored on the hard disk 11 is used. By accessing the cache table, the buffer controller 64 determines the location of the stored data on the hard disk 11 which corresponds to the location of the stored data on the buffer memory 63.
FIG. 6 shows a control process of command enqueuing performed by the conventional interface device.
As shown in FIG. 6, at a start of the control process, the buffer controller 63 determines whether the command is received (S1-1). When the result at the step S1-1 is affirmative, the buffer controller 63 determines whether the received command is valid (S1-2). Otherwise the control of the buffer controller 63 is transferred to a different process.
When the result at the step S1-2 is affirmative, the buffer controller 63 links the received command to the command queue of one of the interface circuits 61 and 62, and the command is retained in one of the interface circuits 61 and 62 (S1-3). Otherwise the buffer controller 63 sends a rejection message to the command source. After the step S1-3 is performed, the control process of FIG. 6 ends.
In the conventional interface device 60, when the write command from one of the computers A and B is received at one of the interface circuits 61 and 62, the writing data from the computer A or the computer B is temporarily stored in the buffer memory 63. After the writing data is stored in the buffer memory 63, the buffer controller 64 informs the command source (the computer A or B) that the execution of the write command is complete. Thereafter, the buffer controller 64 causes the stored data of the buffer memory 63 to be written to the disk 11 by means of the head 13 during an idle time of the head 13. This procedure is called the write-back processing.
When the read command to access the related sector of the disk 11 is issued before the write-back processing is performed, the execution of the read command is deferred and the write-back processing is performed first. Thereafter, the data is read from the hard disk 11.
In the conventional interface device 60, when the write-back processing is performed, a write-back table that provides the correlations between the locations of data stored on the buffer memory 63 and the locations of data stored on the hard disk 11 is used to send a message to the computer A or B. By accessing the write-back table, the buffer controller 64 determines the location of the stored data on the hard disk 11 which corresponds to the location of the stored data on the buffer memory 63.
Both the cache table and the write-back table provide the correlations between the data locations of the buffer memory 23 and the data locations of the hard disk 11. Operational state flags and data validity flags may be added to the cache table and the write-back table, and a common table that is derived from the cache table and the write-back table including the flags may be used.
As described above, because of the data transfer capacity of the buffer memory 63, it is difficult that the conventional interface device 60 in FIG. 5 efficiently carry out the data reading/writing operations in the hard disk drive with the buffer memory 63.